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ST20-C1 bảng dữ liệu(PDF) 70 Page - STMicroelectronics

tên linh kiện ST20-C1
Giải thích chi tiết về linh kiện  Instruction Set Reference Manual
PDF  205 Pages
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
Trang chủ  http://www.st.com
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ST20-C1 bảng dữ liệu(HTML) 70 Page - STMicroelectronics

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6
Exceptions
This chapter describes exceptions and how to use them. The architecture of the
ST20-C1, including the registers and memory arrangement, are described in Chapter
3. A full list of constants and data structures is given in Appendix A.
An
exception is an exceptional event detected by the ST20-C1 core, which causes a
context switch from the normal flow of an executing program. The event triggering the
exception may be generated by software inside the core, in which case it is called a
trap. Otherwise, the event may be a hardware signal from outside the core, in which
case it is called an interrupt, except that the interrupt may attempt to perform a sched-
uling action, which may cause a trap.
When an exception occurs the CPU changes context to an
exception handler, which is
a section of code only executed when an exception occurs. The process state
registers (Areg, Breg, Creg, Iptr, Wptr, Status and Tdesc) are saved while the
exception handler is running, and restored when it returns. Exception handlers for
traps are called
trap handlers and exception handlers for interrupts are called interrupt
handlers. Normal processes which are not exception handlers are known as user
processes.
The exception handler is a transient process. Each exception handler starts execution
with a standard initial state, runs to completion and terminates with an empty work-
space. When the triggering event occurs again, the handler is restarted from its
standard initial state and again runs to completion and terminates.
Exception handlers may be nested to arbitrary depth, but they are not re-entrant, so
care should be taken to ensure that the exception which caused the handler to run
cannot occur while the handler is running, trapped or interrupted. The nesting of
exceptions is illustrated in Figure 6.1.
Figure 6.1 Nested exceptions
User
process
User
process
Exception 1 taken - state of user process saved
Exception 2 taken - state of exception 1 saved
Exception 2 returns - state of exception 1 restored
Exception 1 returns - state of user process restored
Exception 1 executing
Exception 1 executing
Exception 2 executing



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