ST20-C1 datasheet(37/205 Pages) STMICROELECTRONICS

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4 Using ST20-C1 instructions

Each

divstep generates four bits of the unsigned quotient, so eight divsteps are

needed for a full 32-bit unsigned division, and will also generate a remainder. The

result of the division is the integer division rounded towards zero (truncated). The

quotient is left in Breg, and the remainder in Creg, so a rotation pops the quotient into

the Areg.

unsign is used to separate the sign from the magnitude of the operands before

performing the division. Division is then performed on the magnitudes, and the signs

of the results may be derived from the signs of the operands.

Overflow can occur only if the divisor (Areg) is zero, or if the dividend (Breg)is

MostNeg and the divisor is -1. divstep does not detect these cases, and does not set

any status bits, so a check should be applied before performing the division.

The following code sequence performs the integer division

a/b. The signed quotient is

left in Areg.

a; b; ldc 0; arot; unsign;

arot; unsign; cj POS;

ldc 0; rot;

divstep; divstep; divstep; divstep;

rot; not; adc 1;

j END;

POS:

rot;

divstep; divstep; divstep; divstep;

rot;

END:

The following code sequence performs the remainder

a rem b. The signed remainder

is left in Areg.

a; b; ldc 0; rev; unsign;

eqc 2; arot; unsign; cj POS;

divstep; divstep; divstep; divstep;

arot; not; adc 1;

j END;

POS:

rot;

divstep; divstep; divstep; divstep;

arot;

END:

4.4.3

Saturated arithmetic

In saturated arithmetic, when an overflow or underflow occurs the result is set to the

most positive or most negative possible result respectively, instead of the least signifi-

cant bits of the full result. This ensures that the result is as near as possible to the real

value and prevents glitches caused by wrap-around.

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