S7G2 datasheet(17/117 Pages) RENESAS

17 / 117 page

R01DS0262EU0150 Rev.1.50

Page 17 of 117

Sep 24, 2025

S7G2 Datasheet

1. Overview

ETHERC

REF50CK0,

REF50CK1

Input

50-MHz reference clocks. These pins input reference signals for

transmission/reception timing in RMII mode.

RMII0_CRS_DV,

RMII1_CRS_DV

Input

Indicate carrier detection signals and valid receive data on RMII_RXD1 and

RMII_RXD0 in RMII mode

RMII0_TXD0,

RMII0_TXD1,

RMII1_TXD0,

RMII1_TXD1

Output

2-bit transmit data in RMII mode

RMII0_RXD0,

RMII0_RXD1,

RMII1_RXD0,

RMII1_RXD1

Input

2-bit receive data in RMII mode

RMII0_TXD_EN,

RMII1_TXD_EN

Output

Output pins for data transmit enable signals in RMII mode

RMII0_RX_ER,

RMII1_RX_ER

Input

Indicate an error occurred during reception of data in RMII mode

ET0_CRS, ET1_CRS Input

Carrier detection/data reception enable signals

ET0_RX_DV,

ET1_RX_DV

Input

Indicate valid receive data on ETn_ERXD3 to ETn_ERXD0 (n = 0, 1)

ET0_EXOUT,

ET1_EXOUT

Output

General-purpose external output pins

ET0_LINKSTA,

ET1_LINKSTA

Input

Input link status from the PHY-LSI

ET0_ETXD0 to

ET0_ETXD3,

ET1_ETXD0 to

ET1_ETXD3

Output

4 bits of MII transmit data

ET0_ERXD0 to

ET0_ERXD3,

ET1_ERXD0 to

ET1_ERXD3

Input

4 bits of MII receive data

ET0_TX_EN,

ET1_TX_EN

Output

Transmit enable signals. Function as signals indicating that transmit data is

ready on ETn_ETXD3 to ETn_ETXD0 (n = 0, 1).

ET0_TX_ER,

ET1_TX_ER

Output

Transmit error pins. Function as signals notifying the PHY_LSI of an error

during transmission.

ET0_RX_ER,

ET1_RX_ER

Input

Receive error pins. Function as signals to recognize an error during

reception.

ET0_TX_CLK,

ET1_TX_CLK

Input

Transmit clock pins. These pins input reference signals for output timing

from ETn_TX_EN, ETn_ETXD3 to ETn_ETXD0, and ETn_TX_ER (n = 0, 1).

ET0_RX_CLK,

ET1_RX_CLK

Input

Receive clock pins. These pins input reference signals for input timing to

ETn_RX_DV, ETn_ERXD3 to ETn_ERXD0, and ETn_RX_ER (n = 0, 1).

ET0_COL,

ET1_COL

Input

Input collision detection signals

ET0_WOL,

ET1_WOL

Output

Receive Magic packets

ET0_MDC,

ET1_MDC

Output

Output reference clock signals for information transfer through ETn_MDIO

(n = 0, 1)

ETHERC

ET0_MDIO,

ET1_MDIO

I/O

Input or output bidirectional signals for exchange of management data with

PHY-LSI

SDHI/MMC

SD0CLK, SD1CLK

Output

SD/MMC clock output pins

SD0CMD, SD1CMD

I/O

Command output pin and response input signal pins

SD0DAT0 to

SD0DAT7,

SD1DAT0 to

SD1DAT7

I/O

SD/MMC data bus pins

SD0CD, SD1CD

Input

SD/MMC card detection pins

SD0WP, SD1WP

Input

SD/MMC write-protect signals

Table 1.17

Pin functions (4 of 5)

Function

Signal

I/O

Description

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