S7G2 datasheet(44/117 Pages) RENESAS

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R01DS0262EU0150 Rev.1.50

Page 44 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

2.3

AC Characteristics

2.3.1

Frequency

Note 1. FCLK must run at a frequency of at least 4 MHz when programming or erasing the flash memory.

Note 2. See section 9, Clock Generation Circuit in Userʼs Manual for the relationship between the ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK, and BCLK frequencies.

Note 3. When the ADC12 is used, the PCLKC frequency must be at least 1 MHz.

Note 1. Programming or erasing the flash memory is disabled in low-speed mode.

Note 2. See section 9, Clock Generation Circuit in Userʼs Manual for the relationship between the ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK, and BCLK frequencies.

Note 3. When the ADC12 is used, the PCLKC frequency must be set to at least 1 MHz.

Note 1. Programming or erasing the flash memory is disable in Subosc-speed mode.

Note 2. See section 9, Clock Generation Circuit in Userʼs Manual for the relationship between the ICLK, PCLKA, PCLKB,

PCLKC, PCLKD, FCLK, and BCLK frequencies.

Note 3. The ADC12 cannot be used.

Table 2.11

Operation frequency value in high-speed mode

Parameter

Symbol

Min

Typ

Max

Unit

Operation frequency

System clock (ICLK*2)

240

MHz

Peripheral module clock (PCLKA)*2

120

Peripheral module clock (PCLKB)*2

Peripheral module clock (PCLKC)*2

-*3

-60

Peripheral module clock (PCLKD)*2

120

Flash interface clock (FCLK)*2

-*1

-60

External bus clock (BCLK)*2

120

EBCLK pin output

SDCLK pin output

VCC ≥ 3.0 V

120

Table 2.12

Operation frequency value in low-speed mode

Parameter

Symbol

Min

Typ

Max

Unit

Operation frequency

System clock (ICLK)*2

MHz

Peripheral module clock (PCLKA)*2

Peripheral module clock (PCLKB)*2

Peripheral module clock (PCLKC)*2,*3

-*3

-1

Peripheral module clock (PCLKD)*2

Flash interface clock (FCLK)*1, *2

External bus clock (BCLK)

EBCLK pin output

Table 2.13

Operation frequency value in Subosc-speed mode

Parameter

Symbol

Min

Typ

Max

Unit

Operation frequency

System clock (ICLK)*2

29.4

36.1

kHz

Peripheral module clock (PCLKA)*2

36.1

Peripheral module clock (PCLKB)*2

36.1

Peripheral module clock (PCLKC)*2,*3

36.1

Peripheral module clock (PCLKD)*2

36.1

Flash interface clock (FCLK)*1, *2

29.4

36.1

External bus clock (BCLK)*2

36.1

EBCLK pin output

36.1

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