S7G2 datasheet(46/117 Pages) RENESAS

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R01DS0262EU0150 Rev.1.50

Page 46 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

Note 1. When setting up the sub-clock oscillator, ask the oscillator manufacturer for an oscillation evaluation and use the

results as the recommended oscillation stabilization time. After changing the setting in the SOSCCR.SOSTP bit

to start sub-clock operation, only start using the sub-clock oscillator after the sub-clock oscillation stabilization

time elapses with an adequate margin. Two times the oscillation wait time is recommended.

Figure 2.3

EBCLK and SDCLK output timing

Figure 2.4

EXTAL external clock input timing

Figure 2.5

Main clock oscillation start timing

Figure 2.6

LOCO clock oscillation start timing

Table 2.15

Clock timing for the sub-clock oscillator

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

Sub-clock frequency

fSUB

32.768

kHz

Sub-clock oscillation stabilization wait time

tSUBOSCWT

-*1

Figure 2.8

tCf

tCH

tBcyc, tSDcyc

tCr

tCL

EBCLK pin output, SDCLK pin output

tEXH

tEXcyc

EXTAL external clock input

VCC × 0.5

tEXL

tEXr

tEXf

Main clock oscillator output

MOSCCR.MOSTP

Main clock

tMAINOSCWT

LOCO clock

LOCOCR.LCSTP

tLOCOWT

On-chip oscillator output

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