S7G2 datasheet(71/117 Pages) RENESAS

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R01DS0262EU0150 Rev.1.50

Page 71 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

Figure 2.43

SCI simple SPI mode timing for slave when CKPH = 0

Note:

SCL1_A output is not supported in these specifications.

tIICcyc: IIC internal reference clock (IICφ) cycle.

Note 1. Cb indicates the total capacity of the bus line.

Table 2.25

SCI timing (3)

Conditions: For the SCL1_A pins, low drive output is selected in the port drive capability bit in the PmnPFS register.

For other pins, middle drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple IIC

(Standard mode)

SDA input rise time

tSr

1000

Figure 2.44

SDA input fall time

tSf

300

SDA input spike pulse removal time

tSP

04 × tIICcyc

Data input setup time

tSDAS

250

Data input hold time

tSDAH

SCL, SDA capacitive load

Cb*1

400

Simple IIC

(Fast mode)

SDA input rise time

tSr

300

Figure 2.44

SDA input fall time

tSf

300

SDA input spike pulse removal time

tSP

04 × tIICcyc

Data input setup time

tSDAS

100

Data input hold time

tSDAH

SCL, SDA capacitive load

Cb*1

400

tDr, tDf

tSA

tOH

tLEAD

tTD

tLAG

LSB OUT

(Last data)

DATA

MSB OUT

MSB IN

DATA

LSB IN

MSB IN

LSB OUT

tSU

tOD

tREL

MSB OUT

SSn

input

SCKn

CKPOL = 1

input

SCKn

CKPOL = 0

input

MISOn

output

MOSIn

input

(n = 0 to 9)

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