S7G2 datasheet(81/117 Pages) RENESAS

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R01DS0262EU0150 Rev.1.50

Page 81 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

2.3.14

SSI Timing

Figure 2.55

SSI clock input/output timing

Figure 2.56

SSI data transmit and receive timing when SSICR.SCKP = 0

Table 2.30

SSI timing

Conditions:

(1) Middle drive output is selected with the port drive capability bit in the PmnPFS register.

(2) Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the SSI interface,

the AC portion of the electrical characteristics is measured for each group.

Parameter

Symbol

Min

Max

Unit

Test

conditions

SSI

AUDIO_CLK input frequency

tAUDIO

-50

MHz

Output clock period

150

64000

Figure 2.55

Input clock period

150

64000

Clock high pulse width

tHC

Clock low pulse width

tLC

Clock rise time

tRC

-25

Data delay

tDTR

-5

Figure 2.56,

Figure 2.57

Set-up time

tSR

Hold time

tHTR

SSIDATA output delay from WS change time

TDTRW

-25

Figure 2.58

SSISCKn

tHC

tLC

tRC

tI, tO

tSR

tHTR

tDTR

SSISCKn

(Input or Output)

SSIWSn, SSIDATAn

(Input)

SSIWSn, SSIDATAn

(Output)

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