S7G2 datasheet(88/117 Pages) RENESAS

88 / 117 page

R01DS0262EU0150 Rev.1.50

Page 88 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

2.3.18

Graphics LCD Controller Timing

Note 1. Parallel RGB888, 666,565: Maximum 54 MHz

Serial RGB888: Maximum 60 MHz (4x speed)

Note 2. Use pins that have a letter appended to their names, for instance, “_A” or “_B”, to indicate

Note 3. Pins of group“_A” and “_B” combinations are used.

Figure 2.73

LCD_EXTCLK clock input timing

Figure 2.74

LCD_CLK clock output timing

Figure 2.75

Display output timing

Table 2.34

Graphics LCD Controller timing

Conditions:

LCD_CLK: High drive output is selected in the port drive capability bit in the PmnPFS register.

LCD_DATA: Middle drive output is selected in the port drive capability bit in the PmnPFS register.

Parameter

Symbol

Min

Typ

Max

Unit

Test conditions

LCD_EXTCLK input clock frequency

tEcyc

60*1

MHz

Figure 2.73

LCD_EXTCLK input clock low pulse width

tWL

0.45

0.55

tEcyc

LCD_EXTCLK input clock high pulse width

tWH

0.45

0.55

LCD_CLK output clock frequency

tLcyc

60*1

MHz

Figure 2.74

LCD_CLK output clock low pulse width

tLOL

0.4

0.6

tLcyc

Figure 2.74

LCD_CLK output clock high pulse width

tLOH

0.4

0.6

tLcyc

Figure 2.74

LCD data output delay timing _A or _B combinations*2

tDD

-3.5

Figure 2.75

_A and _B combinations*3

-5.0

5.5

1/2 Vcc

VIH VIH

VIL

tDcyc, tEcyc

tWH

tWL

LCD_EXTCLK

tLcyc

tLOL

tLOH

tLOF

tLOR

LCD_CLK

tDD

LCD_DATA00 to

LCD_DATA23,

LCD_TCON0 to

LCD_TCON3

Output on

falling edge

Output on

rising edge

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