S7G2 datasheet(47/117 Pages) RENESAS

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R01DS0262EU0150 Rev.1.50

Page 47 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

Figure 2.7

PLL clock oscillation start timing

Note:

Only operate the PLL is operated after main clock oscillation has stabilized.

Figure 2.8

Sub-clock oscillation start timing

2.3.3

Reset Timing

Table 2.16

Reset timing

Parameter

Symbol

Min

Typ

Max

Unit

Test

conditions

RES pulse width

Power-on

LDO mode

tRESWP

Figure 2.9

DCDC mode

1.5

Deep Software Standby mode

tRESWD

0.6

Figure 2.10

Software Standby mode, Subosc-speed

mode

tRESWS

0.3

All other

tRESW

200

μs

Wait time after RES cancellation

tRESWT

33.4

μs

Figure 2.9

Wait time after internal reset cancellation

(IWDT reset, WDT reset, software reset, SRAM parity error

reset, SRAM DED error reset, bus master MPU error reset, bus

slave MPU error reset, stack pointer error reset)

tRESW2

390

μs-

PLLCR.PLLSTP

OSCSF.PLLSF

PLL clock

tPLLWT

PLL circuit output

Sub-clock oscillator output

SOSCCR.SOSTP

tSUBOSCCWT

Sub-clock

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