S7G2 datasheet(104/117 Pages) RENESAS

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R01DS0262EU0150 Rev.1.50

Page 104 of 117

Sep 24, 2025

S7G2 Datasheet

2. Electrical Characteristics

2.14.2

Data Flash Memory Characteristics

Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times

(n = 125,000), erasing can be performed n times for each block. For example, when 4-byte programming is

performed 16 times for different addresses in 64-byte blocks, and then the entire block is erased, the

reprogram/erase cycle is counted as one. However, programming the same address several times as one

erasure is not enabled. (Overwriting is prohibited.)

Note 2. This is the minimum number of times to guarantee all the characteristics after reprogramming. The guaranteed

range is from 1 to the minimum value.

Note 3. This indicates the characteristics when reprogramming is performed within the specified range, including the

minimum value.

Note 4. This result is obtained from reliability testing.

Table 2.54

Data flash memory characteristics

Conditions: Program or erase: FCLK = 4 to 60 MHz

Read: FCLK ≤ 60 MHz

Parameter

Symbol

FCLK = 4 MHz

20 MHz ≤ FCLK ≤ 60 MHz

Unit

Min

Typ

Max

Min

Typ

Max

Programming time

4-byte

tDP4

0.36

3.8

0.16

1.7

Erasure time

64-byte

tDE64

3.1

1.7

Blank check time

4-byte

tDBC4

μs

Reprogramming/erasure cycle*1

NDPEC

125000*2

---

Suspend delay during programming

tDSPD

264

120

μs

First suspend delay during erasure in

suspend priority mode

tDSESD1

216

120

μs

Second suspend delay during erasure in

suspend priority mode

tDSESD2

300

μs

Suspend delay during erasing in erasure

priority mode

tDSEED

300

μs

Forced stop command

tFD

μs

Data hold time*3 *4

tDDRP

--20

--Year

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