TMS320VC5502 datasheet(3/190 Pages) TI

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Contents

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

Revision History

........................................................................................................................... 2

TMS320VC5502

................................................................................................................. 13

1.1

Features

..................................................................................................................... 13

Introduction

....................................................................................................................... 14

2.1

Description

.................................................................................................................. 14

2.2

Pin Assignments

............................................................................................................ 15

2.2.1

Ball Grid Array (GZZ and ZZZ)

................................................................................ 15

2.2.2

Low-Profile Quad Flatpack (PGF)

............................................................................. 17

2.2.3

Signal Descriptions

.............................................................................................. 19

Functional Overview

........................................................................................................... 31

3.1

Memory

...................................................................................................................... 32

3.1.1

On-Chip ROM

................................................................................................... 32

3.1.2

On-Chip Dual-Access RAM (DARAM)

........................................................................ 33

3.1.3

Instruction Cache

................................................................................................ 33

3.1.4

Memory Map

..................................................................................................... 34

3.1.5

Boot Configuration

............................................................................................... 35

3.2

Peripherals

.................................................................................................................. 35

3.3

Configurable External Ports and Signals

................................................................................ 36

3.3.1

Parallel Port Mux

................................................................................................ 36

3.3.2

Host Port Mux

.................................................................................................... 37

3.3.3

Serial Port 2 Mux

................................................................................................ 38

3.3.4

External Bus Selection Register (XBSR)

..................................................................... 39

3.4

Configuration Examples

................................................................................................... 41

3.5

Timers

........................................................................................................................ 42

3.5.1

Timer Interrupts

.................................................................................................. 43

3.5.2

Timer Pins

........................................................................................................ 44

3.5.3

Timer Signal Selection Register (TSSR)

..................................................................... 45

3.6

Universal Asynchronous Receiver/Transmitter (UART)

............................................................... 46

3.7

Inter-Integrated Circuit (I2C) Module

..................................................................................... 48

3.8

Host-Port Interface (HPI)

.................................................................................................. 49

3.9

Direct Memory Access (DMA) Controller

................................................................................ 50

3.9.1

DMA Channel 0 Control Register (DMA_CCR0)

........................................................... 50

3.10

System Clock Generator

.................................................................................................. 52

3.10.1

Input Clock Source

.............................................................................................. 53

3.10.2

Clock Groups

..................................................................................................... 55

3.10.3

EMIF Input Clock Selection

.................................................................................... 56

3.10.4

Changing the Clock Group Frequencies

..................................................................... 56

3.10.5

PLL Control Registers

.......................................................................................... 58

3.10.6

Reset Sequence

................................................................................................. 69

3.11

Idle Control

.................................................................................................................. 69

3.11.1

Clock Domains

................................................................................................... 70

3.11.2

IDLE Procedures

................................................................................................ 70

3.11.3

Module Behavior at Entering IDLE State

..................................................................... 72

3.11.4

Wake-Up Procedure

............................................................................................ 73

3.11.5

Auto-Wakeup/Idle Function for McBSP and DMA

........................................................... 75

3.11.6

Clock State of Multiplexed Modules

........................................................................... 75

3.11.7

IDLE Control and Status Registers

............................................................................ 76

3.12

General-Purpose I/O (GPIO)

............................................................................................. 84

3.12.1

General-Purpose I/O Port

...................................................................................... 84

3.12.2

Parallel Port General-Purpose I/O (PGPIO)

................................................................. 86

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