TMS320VC5502 datasheet(9/190 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

List of Tables

2-1

201-Terminal GZZ and ZZZ Ball Grid Array Thermal Ball Locations

....................................................... 15

2-2

201-Terminal GZZ and ZZZ Ball Grid Array Ball Assignments

............................................................ 16

2-3

176-Pin PGF Low-Profile Quad Flatpack Pin Assignments

................................................................. 18

2-4

Signal Descriptions

............................................................................................................... 19

3-1

On-Chip ROM Layout

............................................................................................................. 32

3-2

DARAM Blocks

.................................................................................................................... 33

3-3

Boot Configuration Selection Via the BOOTM[2:0] Pins

..................................................................... 35

3-4

TMS320VC5502 Routing of Parallel Port Mux Signals

...................................................................... 37

3-5

TMS320VC5502 Routing of Host Port Mux Signals

.......................................................................... 38

3-6

TMS320VC5502 Routing of Serial Port 2 Mux Signals

...................................................................... 38

3-7

External Bus Selection Register Bit Field Description

........................................................................ 40

3-8

Timer Signal Selection Register Bit Field Description

........................................................................ 45

3-9

Synchronization Control Function

............................................................................................... 51

3-10

Recommended Crystal Parameters

............................................................................................ 54

3-11

Internal Clocks Frequency Ranges

............................................................................................. 55

3-12

PLL Control Registers

............................................................................................................ 58

3-13

PLL Control/Status Register Bit Field Description

............................................................................ 59

3-14

PLL Multiplier Control Register Bit Field Description

......................................................................... 60

3-15

PLL Divider 0 Register Bit Field Description

................................................................................... 61

3-16

PLL Divider 1 Register Bit Field Description

................................................................................... 62

3-17

PLL Divider 2 Register Bit Field Description

................................................................................... 63

3-18

PLL Divider 3 Register Bit Field Description

................................................................................... 64

3-19

Oscillator Divider1 Register Bit Field Description

............................................................................. 65

3-20

Oscillator Wakeup Control Register Bit Field Description

................................................................... 66

3-21

CLKOUT3 Select Register Bit Field Description

.............................................................................. 67

3-22

CLKOUT Selection Register Bit Field Description

............................................................................ 68

3-23

Clock Mode Control Register Bit Field Description

........................................................................... 68

3-24

Number of Reference Clock Cycles Needed Until Program Flow Begins

................................................. 69

3-25

Peripheral Behavior at Entering IDLE State

................................................................................... 72

3-26

Wake-Up Procedures

............................................................................................................. 75

3-27

Clock Domain Memory-Mapped Registers

.................................................................................... 76

3-28

IDLE Configuration Register Bit Field Description

............................................................................ 77

3-29

IDLE Status Register Bit Field Description

.................................................................................... 78

3-30

Peripheral IDLE Control Register Bit Field Description

...................................................................... 80

3-31

Peripheral IDLE Status Register Bit Field Description

....................................................................... 82

3-32

Master IDLE Control Register Bit Field Description

.......................................................................... 83

3-33

Master IDLE Status Register Bit Field Description

........................................................................... 84

3-34

GPIO Direction Register Bit Field Description

................................................................................. 85

3-35

GPIO Data Register Bit Field Description

...................................................................................... 85

List of Tables

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