TMS320VC5502 datasheet(13/190 Pages) TI

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TMS320VC5502

1.1

Features

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

• On-Chip Peripherals

• High-Performance, Low-Power, Fixed-Point

TMS320C55x™ Digital Signal Processor (DSP)

–

Six-Channel Direct Memory Access (DMA)

Controller

–

3.33-/5-ns Instruction Cycle Time

–

Three Multichannel Buffered Serial Ports

–

300-/200-MHz Clock Rate

(McBSPs)

–

16K-Byte Instruction Cache (I-Cache)

–

Programmable Analog Phase-Locked Loop

–

One/Two Instructions Executed per Cycle

(APLL) Clock Generator

–

Dual Multipliers [Up to 600 Million

–

General-Purpose I/O (GPIO) Pins and a

Multiply-Accumulates Per Second

Dedicated Output Pin (XF)

(MMACS)]

–

8-Bit/16-Bit Parallel Host-Port Interface

–

Two Arithmetic/Logic Units (ALUs)

(HPI)

–

One Program Bus, Three Internal

–

Four Timers

Data/Operand Read Buses, and Two

• Two 64-Bit General-Purpose Timers

Internal Data/Operand Write Buses

• 64-Bit Programmable Watchdog Timer

• Instruction Cache (16K Bytes)

• 64-Bit DSP/BIOS™ Counter

• 32K x 16-Bit On-Chip RAM That is Composed

–

Inter-Integrated Circuit (I2C) Interface

of Eight Blocks of 4K × 16-Bit Dual-Access

–

Universal Asynchronous Receiver/

RAM (DARAM) (64K Bytes)

Transmitter (UART)

• 16K × 16-Bit One-Wait-State On-Chip ROM

• On-Chip Scan-Based Emulation Logic

(32K Bytes)

• IEEE Std 1149.1(1) (JTAG) Boundary Scan

• 8M × 16-Bit Maximum Addressable External

Logic

Memory Space

• Packages:

• 32-Bit External Parallel Bus Memory

–

176-Terminal LQFP (Low-Profile Quad

Supporting External Memory Interface (EMIF)

Flatpack) (PGF Suffix)

With General-Purpose Input/Output (GPIO)

–

201-Terminal MicroStar BGA™ (Ball Grid

Capabilities and Glueless Interface to:

Array) (GZZ and ZZZ Suffixes)

–

Asynchronous Static RAM (SRAM)

• 3.3-V I/O Supply Voltage

–

Asynchronous EPROM

• 1.26-V Core Supply Voltage

–

Synchronous DRAM (SDRAM)

–

Synchronous Burst RAM (SBRAM)

• Emulation/Debug Trace Capability Saves Last

16 Program Counter (PC) Discontinuities and

Last 32 PC Values

• Programmable Low-Power Control of Six

(1)

IEEE Standard 1149.1 - 1990 Standard Test Access Port and

Device Functional Domains

Boundary Scan Architecture

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

TMS320C55x, DSP/BIOS, MicroStar BGA, C55x, eXpressDSP, Code Composer Studio, RTDX, XDS510, TMS320C54x, C54x, TMS320,

TMS320C5000 are trademarks of Texas Instruments.

I2C bus is a trademark of Koninklijke Philips Electronics N.V.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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