TMS320VC5502 datasheet(14/190 Pages) TI

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Introduction

2.1

Description

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

This section describes the main features of the TMS320VC5502 and gives a brief description of the

device.

NOTE

This document is designed to be used in conjunction with the TMS320C55x DSP CPU

Reference Guide (literature number SPRU371).

The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x™

DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low

power through increased parallelism and total focus on reduction in power dissipation. The CPU supports

an internal bus structure that is composed of one program bus, three data read buses, two data write

buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to

perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can

perform data transfers independent of the CPU activity.

The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit

multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional

16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel

activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit

(DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The

Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues

instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and

DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline

flushes on execution of conditional instructions.

The 5502 peripheral set includes an external memory interface (EMIF) that provides glueless access to

asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such

as synchronous DRAM and synchronous burst RAM. Additional peripherals include UART, watchdog

timer, and an I-Cache. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless

interface to a variety of industry-standard serial devices, and multichannel communication with up to 128

separately enabled channels. The host-port interface (HPI) is a 8-/16-bit parallel interface used to provide

host processor access to 32K words of internal memory on the 5502. The HPI can be configured in either

multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors.

The DMA controller provides data movement for six independent channel contexts without CPU

intervention. Two general-purpose timers, eight dedicated general-purpose I/O (GPIO) pins, and analog

phase-locked loop (APLL) clock generation are also included.

The 5502 is supported by the industry's award-winning eXpressDSP™, Code Composer Studio™

Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments' algorithm standard, and the

industry's largest third-party network. The Code Composer Studio™ IDE features code generation tools

that include a C Compiler, Visual Linker, simulator, RTDX™, XDS510™ emulation device drivers, and

evaluation modules. The 5502 is also supported by the C55x™ DSP Library, which features more than 50

foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and

board support libraries.

Introduction

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