TMS320VC5502 datasheet(48/190 Pages) TI

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3.7

Inter-Integrated Circuit (I2C) Module

Clock

Prescale

I2CPSC

SYSCLK2

From PLL

Clock Generator

I2CCLKH

Generator

Bit Clock

I2CCLKL

Noise

Filter

I2C Clock

SCL

I2CXSR

I2CDXR

Transmit

Shift

Transmit

Buffer

I2CDRR

Shift

I2CRSR

Receive

Buffer

Receive

Filter

SDA

I2C Data

Noise

I2COAR

I2CSAR

Slave

Address

Control

Address

Own

I2CMDR

I2CCNT

Mode

Data

Count

Source

Interrupt

Status

I2CISRC

I2CSTR

Enable

Interrupt

I2CIER

Interrupt/DMA

I2C Module

Shading denotes control/status registers.

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

The TMS320VC5502 also includes an I2C serial port for control purposes. Features of the I2C port include:

• Compatibility with Philips' I2C-Bus Specification, Version 2.1 (January 2000)

• Fast mode up to 400 Kbps (no fail-safe I/O buffers)

• Noise filters (on the SDA and SCL pins) to suppress noise of 50 ns or less (I2C module clock must be

in the range of 7 MHz to 12 MHz)

• 7-bit and 10-bit device addressing modes

• Master (transmit/receive) and slave (transmit/receive) functionality

• Events: DMA, interrupt, or polling

• Slew-rate limited open-drain output buffers

The I2C module clock must be in the range of 7 MHz to 12 MHz. This is necessary for the proper

operation of the I2C module.

NOTE

For

additional

information,

see

the

TMS320VC5501/5502/5503/5507/5509

DSP Inter-Integrated Circuit (I2C) Module Reference Guide (literature number SPRU146).

Figure 3-10 is a block diagram of the I2C module.

Figure 3-10. I2C Module Block Diagram

Functional Overview

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