TMS320VC5502 datasheet(63/190 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

3.10.5.5 PLL Divider2 Register (PLLDIV2) for SYSCLK2

This register controls the value of the divider D2 for SYSCLK2. It is in both the BYPASS and PLL paths.

D2EN

Reserved

R/W, 1

R, 0000000

Reserved

PLLDIV2

R, 000

R/W, 00011

LEGEND: R = Read, W = Write, n = value at reset

Figure 3-19. PLL Divider 2 Register Layout (0x1C8E)

Table 3-17. PLL Divider 2 Register Bit Field Description

BIT NAME

BIT NO.

ACCESS

RESET VALUE

DESCRIPTION

D2EN

R/W

Divider D2 enable

•

D2EN = 0: Divider 2 disabled

•

D2EN = 1: Divider 2 enabled

Reserved

14:5

0000000000

Reserved. Reads return 0. Writes have no effect.

PLLDIV2

4:0

R/W

00011

Divider D2 ratio (SYSCLK2 divider)

•

PLLDIV2 = 00000: Divide by 1

•

PLLDIV2 = 00001: Divide by 2

•

PLLDIV2 = 00010: Reserved

•

PLLDIV2 = 00011: Divide by 4

•

PLLDIV2 = 00100–11111: Reserved

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