TMS320VC5502 datasheet(53/190 Pages) TI

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3.10.1

Input Clock Source

1C2

) C2)

X2/CLKIN

Crystal

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

The clock input to the 5502 can be sourced from either an externally generated 3.3-V clock input on the

X2/CLKIN pin, or from the on-chip oscillator if an external crystal circuit is attached to the device as shown

in Figure 3-13. The CLKMD0 bit of the Clock Mode Control Register (CLKMD) determines which clock,

either OSCOUT or X2/CLKIN, is used as an input clock source to the DSP. If GPIO4 is low at reset, the

CLKMD0 bit of the Clock Mode Control Register (CLKMD) will be set to '0' and the internal oscillator and

the external crystal will generate the input clock to the DSP. If GPIO4 is high, the CLKMD0 bit will be set

to '1' and the input clock will be taken directly from the X2/CLKIN pin.

The input clock source to the DSP can be directly used to generate the clocks to other parts of the system

(Bypass Mode) or it can be multiplied by a value from 2 to 15 and divided by a value from 1 to 32 to

achieve a desired frequency (PLL Mode). The PLLEN bit of the PLL Control/Status Register (PLLCSR) is

used to select between the PLL and bypass modes of the clock generator.

The clock generated through either the PLL Mode or the Bypass Mode can be further divided down to

generate a clock source for other parts of the system, or Clock Groups. Clock groups allow for lower

power and performance optimization since the frequency of groups with no high-speed requirements can

be set to one-fourth or one-half the frequency of other groups. A description of the different clock groups

included in the 5502 and the procedure for changing the operating frequency for those clock groups are

described later in this section.

3.10.1.1 Internal System Oscillator With External Crystal

The 5502 includes an internal oscillator which can be used in conjunction with an external crystal to

generate the input clock to the DSP. The oscillator requires an external crystal connected across the X1

and X2/CLKIN pins. If the internal oscillator is not used, an external clock source must be applied to the

X2/CLKIN pin and the X1 pin should be left unconnected. Since the internal oscillator can be used as a

clock source to the PLL, the crystal oscillation frequency can be multiplied to generate the input clock to

the different clock groups of the DSP.

The crystal should be in fundamental-mode operation, and parallel resonant, with a maximum effective

series resistance (ESR) as specified in Table 3-10. The connection of the required circuit is shown in

Figure 3-13. Under some conditions, all the components shown are not required. The capacitors, C1 and

C2, should be chosen such that the equation below is satisfied. CL in the equation is the load specified for

the crystal that is also specified in Table 3-10.

Figure 3-13. Internal System Oscillator With External Crystal

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