TMS320VC5502 datasheet(6/190 Pages) TI

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TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

List of Figures

2-1

201-Terminal GZZ and ZZZ Ball Grid Array (Bottom View)

................................................................. 15

2-2

176-Pin PGF Low-Profile Quad Flatpack (Top View)

........................................................................ 17

3-1

TMS320VC5502 Functional Block Diagram

................................................................................... 31

3-2

TMS320VC5502 Memory Map

.................................................................................................. 34

3-3

External Bus Selection Register Layout (0x6C00)

............................................................................ 39

3-4

Configuration Example A

(GPIO6 = 1 and GPIO7 = 1 at Reset)

.......................................................................................... 41

3-5

Configuration Example B

(GPIO6 = 0 and GPIO7 = 0 at Reset)

.......................................................................................... 42

3-6

Timer Interrupts

.................................................................................................................... 43

3-7

Timer Pins

.......................................................................................................................... 44

3-8

Timer Signal Selection Register Layout (0x8000)

............................................................................ 45

3-9

UART Functional Block Diagram

................................................................................................ 47

3-10

I2C Module Block Diagram

....................................................................................................... 48

3-11

DMA Channel 0 Control Register Layout (0x0C01)

.......................................................................... 50

3-12

System Clock Generator

......................................................................................................... 52

3-13

Internal System Oscillator With External Crystal

.............................................................................. 53

3-14

Clock Generator Registers

....................................................................................................... 57

3-15

PLL Control/Status Register Layout (0x1C80)

................................................................................ 59

3-16

PLL Multiplier Control Register Layout (0x1C88)

............................................................................. 60

3-17

PLL Divider 0 Register Layout (0x1C8A)

...................................................................................... 61

3-18

PLL Divider 1 Register Layout (0x1C8C)

...................................................................................... 62

3-19

PLL Divider 2 Register Layout (0x1C8E)

...................................................................................... 63

3-20

PLL Divider 3 Register Layout (0x1C90)

....................................................................................... 64

3-21

Oscillator Divider1 Register Layout (0x1C92)

................................................................................. 64

3-22

Oscillator Wakeup Control Register Layout (0x1C98)

....................................................................... 66

3-23

CLKOUT3 Select Register Layout (0x1C82)

.................................................................................. 67

3-24

CLKOUT Selection Register Layout (0x8400)

................................................................................. 68

3-25

Clock Mode Control Register Layout (0x8C00)

............................................................................... 68

3-26

IDLE Configuration Register Layout (0x0001)

................................................................................. 76

3-27

IDLE Status Register Layout (0x0002)

......................................................................................... 78

3-28

Peripheral IDLE Control Register Layout (0x9400)

........................................................................... 79

3-29

Peripheral IDLE Status Register Layout (0x9401)

............................................................................ 82

3-30

Master IDLE Control Register Layout (0x9402)

............................................................................... 83

3-31

Master IDLE Status Register Layout (0x9403)

................................................................................ 84

3-32

GPIO Direction Register Layout (0x3400)

..................................................................................... 85

3-33

GPIO Data Register Layout (0x3401)

.......................................................................................... 85

3-34

Parallel GPIO Enable Register 0 Layout (0x4400)

........................................................................... 87

3-35

Parallel GPIO Direction Register 0 Layout (0x4401)

......................................................................... 88

3-36

Parallel GPIO Data Register 0 Layout (0x4402)

.............................................................................. 89

List of Figures

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