TMS320VC5502 datasheet(39/190 Pages) TI

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3.3.4

External Bus Selection Register (XBSR)

TMS320VC5502

Fixed-Point Digital Signal Processor

SPRS166J – APRIL 2001 – REVISED AUGUST 2006

The External Bus Selection Register controls the mode of the Parallel Port Mux, Host Port Mux, and the

Serial Port 2 Mux. The Parallel Port Mux can be configured to support the 32-bit EMIF or to support the

HPI in 16-bit (non-multiplexed) mode and parallel general-purpose I/O. The Host Port Mux can be

configured to support the HPI in 8-bit (multiplexed) mode or parallel general-purpose I/O (PGPIO). The

Serial Port 2 Mux can be configured to support either the McBSP2 or the UART and general-purpose I/O.

The XBSR configures the Parallel Port Mux and the Host Port Mux at reset based on the state of the

GPIO6 pin at reset. When GPIO6 is high at reset, the Parallel Port Mux will be configured to support the

32-bit EMIF and the Host Port Mux will be configured to support the HPI in 8-bit (multiplexed) mode. When

GPIO6 is low at reset, the Parallel Port Mux will be configured to support the HPI in 16-bit

(non-multiplexed) mode and parallel general-purpose I/O (PGPIO) and the Host Port Mux will be

configured to support parallel general-purpose I/O. The Paralle/Host Port Mux Mode bit of the XBSR will

reflect the mode selected for the Parallel and Host Port Muxes. (1)

The XBSR configures the Serial Port 2 Mux based on the state of the GPIO7 pin at reset. When GPIO7 is

high at reset, the Serial Port 2 Mux will be configured to support the McBSP2. When GPIO7 is low at

reset, the Serial Port 2 Mux will be configured to support the UART and general-purpose I/O (PGPIO). The

Serial Port 2 Mux Mode bit of the XBSR will reflect the mode selected for the Serial Port 2 Mux. (1)

The clock to the McBSP2, UART, and EMIF modules is disabled automatically when these modules are

not selected through the External Bus Selection Register. Note that any accesses to disabled modules will

result in a bus error if the PERITOEN bit of the Time-Out Control Register is set to 1.

(1)

Modifying the XBSR to change the mode of the Parallel Port Mux, Host Port Mux, and Serial Port 2 Mux after the 5502 has been

brought out of reset is not supported.

Reserved

R, 00000000

Serial Port 2

Parallel /Host

Reserved

Reserved(1)

Reserved

Mux Mode

Port Mux Mode

R, 0000

R/W, 0

R/W, GPIO7

R, 0

R/W, GPIO6

LEGEND: R = Read, W = Write, n = value at reset

(1)

This reserved bit must be kept as zero during any writes to XBSR.

Figure 3-3. External Bus Selection Register Layout (0x6C00)

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