HCS08 datasheet(132/198 Pages) NXP

132 / 198 page

Internal Clock Source (S08ICSV1)

MC9S08QD4 Series MCU Data Sheet, Rev. 6

132

Freescale Semiconductor

9.4.7

Fixed Frequency Clock

The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source for

peripheral modules. The ICS provides an output signal (ICSFFE) which indicates when the ICS is

providing ICSOUT frequencies four times or greater than the divided FLL reference clock (ICSFFCLK).

In FLL engaged mode (FEI and FEE) this is always true and ICSFFE is always high. In ICS bypass modes,

ICSFFE will get asserted for the following combinations of BDIV and RDIV values:

•

BDIV=00 (divide by 1), RDIV

≥ 010

•

BDIV=01 (divide by 2), RDIV

≥ 011

•

BDIV=10 (divide by 4), RDIV

≥ 100

•

BDIV=11 (divide by 8), RDIV

≥ 101

9.5

Module Initialization

This section describes how to initialize and configure the ICS module. The following sections contain two

initialization examples.

9.5.1

ICS Module Initialization Sequence

The ICS comes out of POR configured for FEI mode with the BDIV set for divide-by 2. The internal

reference will stabilize in tIRST microseconds before the FLL can acquire lock. As soon as the internal

reference is stable, the FLL will acquire lock in tAcquire milliseconds.

Upon POR, the internal reference will require trimming to guarantee an accurate clock. Freescale

recommends using FLASH location 0xFFAE for storing the fine trim bit, FTRIM in the ICSSC register,

and 0xFFAF for storing the 8-bit trim value for the ICSTRM register. The MCU will not automatically

copy the values in these FLASH locations to the respective registers. Therefore, user code must copy these

values from FLASH to the registers.

NOTE

The BDIV value must not be changed to divide-by 1 without first trimming

the internal reference. Failure to do so could result in the MCU running out

of specification.

9.5.1.1

Initialization Sequence, Internal Clock Mode to External Clock Mode

To change from FEI or FBI clock modes to FEE or FBE clock modes, follow this procedure:

1. Enable the external clock source by setting the appropriate bits in ICSC2.

— If FBE will be the selected mode, also set the LP bit at this time to minimize power

consumption.

2. If necessary, wait for the external clock source to stabilize. Typical crystal startup times are given

in Electrical Characteristics appendix. If EREFS is set in step 1, then the OSCINIT bit will set as

soon as the oscillator has completed the initialization cycles.

3. Write to ICSC1 to select the clock mode.

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