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VS6724 bảng dữ liệu(PDF) 38 Page - STMicroelectronics

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VS6724 bảng dữ liệu(HTML) 38 Page - STMicroelectronics

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Functional description
VS6724
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Figure 23.
QCLK options
The YCbCr, RGB and Bayer timings are represented on
Figure 24, with the associated
qualifying PCLK clock. The output clock rate is effectively halved for the Bayer 8-bit and
YCbCr4:0:0 modes where only one byte of output data is required per pixel.
Figure 24. Qualification clock
In practice the user is likely to require to write some additional setup information prior to
receive the required data output.
D0
D1
D2
data
Negative edge
PCLK
Negative edge
Positive edge
Positive edge
None-active
level - Low
None-active
level - High
Yn
Cbn,n+1
Yn+1
Crn,n+1
YCbCr
Data[7:0]
Data[7:0]
RGB565
Cbn+2,n+3
RGB444
Pix0_lsb
Pix0_msb
Pix1_lsb
Pix1_msb
Pix2_lsb
Data[7:0]
Bayer 10-Bit
Pix0_lsb
Pix0_msb
Pix1_lsb
Pix1_msb
Pix2_lsb
Data[7:0]
Bayer 8-Bit
Pix0
Pix1
Pix2
Data[7:0]
YCbCr 4:0:0
Pix0
Pix1
Pix2
16-bit data output formats - 2 bytes per pixel
8-bit data output formats- 1 byte per pixel
PCLK
PCLK
PCLK
PCLK
PCLK



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