PM7344 datasheet(151/293 Pages) PMC

151 / 293 page

PM7344 S/UNI-MPH

DATA SHEET

PMC-950449

ISSUE 6

MULTI-PHY USER NETWORK INTERFACE

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

135

Registers 038H, 138H, 238H and 338H: RFDL Configuration

Bit

Type

Function

Default

Bit 7

Unused

Bit 6

Unused

Bit 5

Unused

Bit 4

Unused

Bit 3

Unused

Bit 2

Unused

Bit 1

R/W

Bit 0

R/W

EN:

The enable bit (EN) controls the overall operation of the RFDL. When set,

the RDFL is enabled; when reset, the RFDL is disabled. When the block is

disabled, the FIFO and interrupts are all cleared; however, the programming

of the Enable/Status Register is not affected. When the block is enabled, it

will immediately begin looking for flags.

TR:

Setting the terminate reception bit (TR) forces the RFDL to immediately

terminate the reception of the current HDLC frame, empty the FIFO, clear the

interrupts, and begin searching for a new flag sequence. The RFDL handles

the TR input in the same manner as if the EN bit had been cleared and then

set. The TR bit in the Configuration register will reset itself after a rising and

falling edge have occurred on the datalink clock input to the RFDL once the

write to this register has completed. If the Configuration register is read after

this time, the TR bit value returned will be zero.

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