MC68HC908GR4MP datasheet(196/286 Pages) FREESCALE

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System Integration Module (SIM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

196

Freescale Semiconductor

19.5.1.1 Hardware Interrupts

A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after

completion of the current instruction. When the current instruction is complete, the SIM checks all pending

hardware interrupts. If interrupts are not masked (I bit clear in the condition code register) and if the

corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next

instruction is fetched and executed.

If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is

serviced first. Figure 19-11 demonstrates what happens when two interrupts are pending. If an interrupt

is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the

LDA instruction is executed.

Figure 19-11

. Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI instructions. However, in the case of the

INT1 RTI prefetch, this is a redundant operation.

NOTE

To maintain compatibility with the M6805 Family, the H register is not

pushed on the stack during interrupt entry. If the interrupt service routine

modifies the H register or uses the indexed addressing mode, software

should save the H register and then restore it prior to exiting the routine.

19.5.1.2 SWI Instruction

The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the

interrupt mask (I bit) in the condition code register.

NOTE

A software interrupt pushes PC onto the stack. A software interrupt does

not push PC – 1, as a hardware interrupt does.

CLI

LDA

INT1

PULH

RTI

INT2

BACKGROUND

#$FF

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH

RTI

PSHH

INT2 INTERRUPT SERVICE ROUTINE

ROUTINE

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