MC68HC908GR4MP datasheet(192/286 Pages) FREESCALE

192 / 286 page

System Integration Module (SIM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

192

Freescale Semiconductor

19.3.2.1 Power-On Reset

When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate

that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out

4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released

from reset to allow the reset vector sequence to occur.

At power-on, these events occur:

•

A POR pulse is generated.

•

The internal reset signal is asserted.

•

The SIM enables CGMOUT.

•

Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow

stabilization of the oscillator.

•The RST pin is driven low during the oscillator stabilization time.

•

The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are

cleared.

Figure 19-7. POR Recovery

19.3.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an

internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down

the RST pin for all internal reset sources.

The COP module is disabled if the RST pin or the IRQ pin is held at Vtst while the MCU is in monitor mode.

The COP module can be disabled only through combinational logic conditioned with the high voltage

signal on the RST or the IRQ pin. This prevents the COP from becoming disabled as a result of external

noise. During a break state, Vtst on the RST pin disables the COP module.

PORRST

OSC1

CGMXCLK

CGMOUT

RST

IAB

4096

CYCLES

$FFFE

$FFFF

IRST

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