MC68HC908GR4MP datasheet(41/286 Pages) FREESCALE

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Timebase Module (TBM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

3.12.2 Stop Mode

The TIM is inactive in stop mode. The STOP instruction does not affect register states or the state of the

TIM counter. TIM operation resumes when the MCU exits stop mode after an external interrupt.

3.13 Timebase Module (TBM)

3.13.1 Wait Mode

The timebase module remains active after execution of the WAIT instruction. In wait mode, the timebase

If the timebase functions are not required during wait mode, reduce the power consumption by stopping

the timebase before enabling the WAIT instruction.

3.13.2 Stop Mode

The timebase module may remain active after execution of the STOP instruction if the oscillator has been

enabled to operate during stop mode through the OSCSTOPEN bit in the CONFIG register. The timebase

module can be used in this mode to generate a periodic wakeup from stop mode.

If the oscillator has not been enabled to operate in stop mode, the timebase module will not be active

during stop mode. In stop mode, the timebase register is not accessible by the CPU.

If the timebase functions are not required during stop mode, reduce the power consumption by stopping

the timebase before enabling the STOP instruction.

3.14 Exiting Stop Mode

These events restart the system clocks and load the program counter with the reset vector or with an

interrupt vector:

•

External reset — A 0 on the RST pin resets the MCU and loads the program counter with the

contents of locations $FFFE and $FFFF.

•

External interrupt — A high-to-low transition on an external interrupt pin loads the program counter

with the contents of locations:

–

$FFFA and $FFFB; IRQ pin

–

$FFDE and $FFDF; keyboard interrupt pins

•

Low-voltage inhibit (LVI) reset — A power supply voltage below the LVItripf voltage resets the MCU

and loads the program counter with the contents of locations $FFFE and $FFFF.

•

Break interrupt — A break interrupt loads the program counter with the contents of locations $FFFC

and $FFFD.

•

Timebase module (TBM) interrupt — A TBM interrupt loads the program counter with the contents

of locations $FFDC and $FFDD when the timebase counter has rolled over. This allows the TBM

to generate a periodic wakeup from stop mode.

Upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. A 12-bit

stop recovery counter inhibits the system clocks for 4096 CGMXCLK cycles after the reset or external

interrupt.

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