MC68HC908GR4MP datasheet(51/286 Pages) FREESCALE

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Interrupts

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

4.3.2.2 Break Interrupt

The break module causes the CPU to execute an SWI instruction at a software-programmable break

point.

4.3.2.3 IRQ Pin

A logic 0 on the IRQ1 pin latches an external interrupt request.

4.3.2.4 CGM (Clock Generator Module)

The CGM can generate a CPU interrupt request every time the phase-locked loop circuit (PLL) enters or

leaves the locked state. When the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt

enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the PLL bandwidth control register.

PLLF is in the PLL control register.

4.3.2.5 TIM1 (Timer Interface Module 1)

TIM1 CPU interrupt sources:

•

TIM1 overflow flag (TOF) — The TOF bit is set when the TIM1 counter value rolls over to $0000

after matching the value in the TIM1 counter modulo registers. The TIM1 overflow interrupt enable

bit, TOIE, enables TIM1 overflow CPU interrupt requests. TOF and TOIE are in the TIM1 status

and control register.

•

TIM1 channel flags (CH1F–CH0F) — The CHxF bit is set when an input capture or output compare

occurs on channel x. The channel x interrupt enable bit, CHxIE, enables channel x TIM1 CPU

interrupt requests. CHxF and CHxIE are in the TIM1 channel x status and control register.

4.3.2.6 TIM2 (Timer Interface Module 2)

TIM2 CPU interrupt sources:

•

TIM2 overflow flag (TOF) — The TOF bit is set when the TIM2 counter value rolls over to $0000

after matching the value in the TIM2 counter modulo registers. The TIM2 overflow interrupt enable

bit, TOIE, enables TIM2 overflow CPU interrupt requests. TOF and TOIE are in the TIM2 status

and control register.

•

TIM2 channel flag (CH0F) — The CH0F bit is set when an input capture or output compare occurs

on channel 0. The channel 0 interrupt enable bit, CH0IE, enables channel 0 TIM2 CPU interrupt

requests. CH0F and CH0IE are in the TIM2 channel 0 status and control register.

4.3.2.7 SPI (Serial Peripheral Interface)

SPI CPU interrupt sources:

•

SPI receiver full bit (SPRF) — The SPRF bit is set every time a byte transfers from the shift register

to the receive data register. The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU

interrupt requests. SPRF is in the SPI status and control register and SPRIE is in the SPI control

•

SPI transmitter empty (SPTE) — The SPTE bit is set every time a byte transfers from the transmit

data register to the shift register. The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU

interrupt requests. SPTE is in the SPI status and control register and SPTIE is in the SPI control

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