MC68HC908GR4MP datasheet(59/286 Pages) FREESCALE

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I/O Registers

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

AIEN — ADC Interrupt Enable Bit

When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is

cleared when the data register is read or the status/control register is written. Reset clears the AIEN bit.

1 = ADC interrupt enabled

0 = ADC interrupt disabled

ADCO — ADC Continuous Conversion Bit

When this bit is set, the ADC will convert samples continuously and update the ADR register at the end

of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit.

1 = Continuous ADC conversion

0 = One ADC conversion

ADCH4–ADCH0 — ADC Channel Select Bits

ADCH4–ADCH0 form a 5-bit field which is used to select one of 16 ADC channels. Only six channels,

AD5–AD0, are available on this MCU. The channels are detailed in Table 5-1. Care should be taken

when using a port pin as both an analog and digital input simultaneously to prevent switching noise

from corrupting the analog signal. See Table 5-1.

The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for

reduced power consumption for the MCU when the ADC is not being used.

NOTE

Recovery from the disabled state requires one conversion cycle to stabilize.

The voltage levels supplied from internal reference nodes, as specified in Table 5-1, are used to verify the

operation of the ADC converter both in production test and for user applications.

Table 5-1. Mux Channel Select

ADCH4

ADCH3

ADCH2

ADCH1

ADCH0

Input Select

000

PTB0/ATD0

000

PTB1/ATD1

001

PTB2/ATD2

001

PTB3/ATD3

010

PTB4/ATD4

010

PTB5/ATD5

011

Reserved

011

Reserved

↓↓

↓↓↓

Reserved

101

Reserved

110

Reserved

110

VREFH

111

VREFL

ADC power off

NOTE: If an unknown channel is selected it should be made clear what value the user will read

from the ADC Data Register, unknown or reserved is not specific enough.

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