MC68HC908GR4MP datasheet(78/286 Pages) FREESCALE

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Clock Generator Module (CGMC)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

7.4.4 PLL Analog Power Pin (VDDA)

VDDA is a power pin used by the analog portions of the PLL. Connect the VDDA pin to the same voltage

potential as the VDD pin.

NOTE

Route VDDA carefully for maximum noise immunity and place bypass

capacitors as close as possible to the package.

7.4.5 PLL Analog Ground Pin (VSSA)

VSSA is a ground pin used by the analog portions of the PLL. Connect the VSSA pin to the same voltage

potential as the VSS pin.

NOTE

Route VSSA carefully for maximum noise immunity and place bypass

capacitors as close as possible to the package.

7.4.6 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM) and enables the oscillator and

PLL.

7.4.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB)

OSCSTOPENB is a bit in the CONFIG register that enables the oscillator to continue operating during

stop mode. If this bit is set, the Oscillator continues running during stop mode. If this bit is not set (default),

the oscillator is controlled by the SIMOSCEN signal which will disable the oscillator during stop mode.

7.4.8 Crystal Output Frequency Signal (CGMXCLK)

CGMXCLK is the crystal oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes

directly from the crystal oscillator circuit. Figure 7-2 shows only the logical relation of CGMXCLK to OSC1

and OSC2 and may not represent the actual circuitry. The duty cycle of CGMXCLK is unknown and may

depend on the crystal and other external factors. Also, the frequency and amplitude of CGMXCLK can be

unstable at startup.

7.4.9 CGMC Base Clock Output (CGMOUT)

CGMOUT is the clock output of the CGMC. This signal goes to the SIM, which generates the MCU clocks.

CGMOUT is a 50 percent duty cycle clock running at twice the bus frequency. CGMOUT is software

programmable to be either the oscillator output, CGMXCLK, divided by two or the VCO clock, CGMVCLK,

divided by two.

7.4.10 CGMC CPU Interrupt (CGMINT)

CGMINT is the interrupt signal generated by the PLL lock detector.

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