MC68HC908GR4MP datasheet(82/286 Pages) FREESCALE

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Clock Generator Module (CGMC)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

7.5.2 PLL Bandwidth Control Register

The PLL bandwidth control register (PBWC):

•

Selects automatic or manual (software-controlled) bandwidth control mode

•

Indicates when the PLL is locked

•

In automatic bandwidth control mode, indicates when the PLL is in acquisition or tracking mode

•

In manual operation, forces the PLL into acquisition or tracking mode

AUTO — Automatic Bandwidth Control Bit

This read/write bit selects automatic or manual bandwidth control. When initializing the PLL for manual

operation (AUTO = 0), clear the ACQ bit before turning on the PLL. Reset clears the AUTO bit.

1 = Automatic bandwidth control

0 = Manual bandwidth control

LOCK — Lock Indicator Bit

When the AUTO bit is set, LOCK is a read-only bit that becomes set when the VCO clock, CGMVCLK,

is locked (running at the programmed frequency). When the AUTO bit is clear, LOCK reads as 0 and

has no meaning. The write one function of this bit is reserved for test, so this bit must always be written

a 0. Reset clears the LOCK bit.

1 = VCO frequency correct or locked

0 = VCO frequency incorrect or unlocked

ACQ — Acquisition Mode Bit

When the AUTO bit is set, ACQ is a read-only bit that indicates whether the PLL is in acquisition mode

or tracking mode. When the AUTO bit is clear, ACQ is a read/write bit that controls whether the PLL is

in acquisition or tracking mode.

In automatic bandwidth control mode (AUTO = 1), the last-written value from manual operation is

stored in a temporary location and is recovered when manual operation resumes. Reset clears this bit,

enabling acquisition mode.

1 = Tracking mode

0 = Acquisition mode

Address:

$0037

Bit 7

654321

Bit 0

Read:

AUTO

LOCK

ACQ

0000

Write:

Reset:

00000000

= Unimplemented

R= Reserved

Figure 7-5. PLL Bandwidth Control Register (PBWC)

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