MC68HC908GR4MP datasheet(53/286 Pages) FREESCALE

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Interrupts

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

4.3.2.9 KBD0–KBD4 Pins

A 0 on a keyboard interrupt pin latches an external interrupt request.

4.3.2.10 ADC (Analog-to-Digital Converter)

When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC

conversion. The COCO/IDMAS bit is not used as a conversion complete flag when interrupts are enabled.

4.3.2.11 TBM (Timebase Module)

The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2–TBR0. When

the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase

interrupt, the counter chain overflow will generate a CPU interrupt request.

Interrupts must be acknowledged by writing a logic 1 to the TACK bit.

4.3.3 Interrupt Status Registers

The flags in the interrupt status registers identify maskable interrupt sources. Table 4-2 summarizes the

interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be

useful for debugging.

Table 4-2. Interrupt Source Flags

Interrupt Source

Interrupt Status Register Flag

Reset

—

SWI instruction

—

IRQ pin

IF1

CGM (PLL)

IF2

TIM1 channel 0

IF3

TIM1 channel 1

IF4

TIM1 overflow

IF5

TIM2 channel 0

IF6

Reserved

IF7

TIM2 overflow

IF8

SPI receive

IF9

SPI transmit

IF10

SCI error

IF11

SCI receive

IF12

SCI transmit

IF13

Keyboard

IF14

ADC conversion complete

IF15

Timebase

IF16

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