MC68HC908GR4MP datasheet(95/286 Pages) FREESCALE

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COP Control Register

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

9.3.7 COPD (COP Disable)

The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register. See

Chapter 8 Configuration Register (CONFIG).

9.3.8 COPRS (COP Rate Select)

The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register. See

Chapter 8 Configuration Register (CONFIG).

9.4 COP Control Register

The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to

$FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low

byte of the reset vector.

9.5 Interrupts

The COP does not generate CPU interrupt requests.

9.6 Monitor Mode

When monitor mode is entered with VTST on the IRQ pin, the COP is disabled as long as VTST remains

on the IRQ pin or the RST pin. When monitor mode is entered by having blank reset vectors and not

having VTST on the IRQ pin, the COP is automatically disabled until a POR occurs.

9.7 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-consumption standby modes.

9.7.1 Wait Mode

The COP remains active during wait mode. If COP is enabled, a reset will occur at COP timeout.

9.7.2 Stop Mode

Stop mode turns off the CGMXCLK input to the COP and clears the COP prescaler. Service the COP

immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering

or exiting stop mode.

Address: $FFFF

Bit 7

654

Bit 0

Read:

Low byte of reset vector

Write:

Clear COP counter

Reset:

Unaffected by reset

Figure 9-2. COP Control Register (COPCTL)

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