MC68HC908GR4MP datasheet(200/286 Pages) FREESCALE

200 / 286 page

System Integration Module (SIM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

200

Freescale Semiconductor

Figure 19-16 and Figure 19-17 show the timing for WAIT recovery.

Figure 19-16. Wait Recovery from Interrupt or Break

Figure 19-17. Wait Recovery from Internal Reset

19.6.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a

module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery

time has elapsed. Reset or break also causes an exit from stop mode.

The SIM disables the clock generator module outputs (CGMOUT and CGMXCLK) in stop mode, stopping

the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the CONFIG register

(MOR). If SSREC is set, stop recovery is reduced from the normal delay of 4096 CGMXCLK cycles down

to 32. This is ideal for applications using canned oscillators that do not require long startup times from

stop mode.

NOTE

External crystal applications should use the full stop recovery time by

clearing the SSREC bit unless the OSCSTOPENB bit is set in the

configuration register.

The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop

recovery. It is then used to time the recovery period. Figure 19-18 shows stop mode entry timing.

NOTE

To minimize stop current, all pins configured as inputs should be driven to

a 1 or 0.

$6E0C

$6E0B

$00FF

$00FE

$00FD

$00FC

$A6

$01

$0B

$6E

$A6

IAB

IDB

EXITSTOPWAIT

Note: EXITSTOPWAIT = RST pin, CPU interrupt, or break interrupt

IAB

IDB

RST

$A6

$6E0B

RST VCT H RST VCT L

$A6

CGMXCLK

CYCLES

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