UPD77533 datasheet(76/104 Pages) RENESAS

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Data Sheet S15671EJ4V0DS

µµµµPD77533

System Interface

• Reset (RESETB)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

RESETB low-level width

tRWLP

On power application

Note 1

73.2

−−

tRWLS

In STOP mode

73.2

−−

tRWL

In normal mode

73.2

−

In HALT mode

1170

RESETB recovery time

tRRE

In normal mode

73.2

−−

In HALT mode

1170

Output initialization time 1

Note 2

(from RESETB

↓)

tDR1

MA19 to MA0, MCSB, MRDB,

MWRB

−−

tGCIC + 30

Output initialization time 2

Note 2

(from RESETB

↓)

tDR2

MD15 to MD0

−−

tGCIC + 30

Output initialization time 3

Note 2

(from RESETB

↓)

tDR3

RTS, TXD, ADSCK

−−

tGCIC + 30

Output initialization time 4

Note 2

(from RESETB

↓)

tDR4

AGC, DCOFF

−−

tGCIC + 30

Output initialization time 5

Note 2

(from RESETB

↓)

tDR5

RFON

−−

tGCIC + 30

Notes

Measurement of EVDD, IVDD, and AVDD starts at the point they reach the guaranteed operating

voltage after power application.

Output pin signals are undefined from RESETB input to this output initialization time. Also, when

the

µPD77533 is restored from the STOP mode at power application, measurement starts from the

point at which the internal clock starts oscillating stably.

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