TMPR4925 datasheet(246/590 Pages) TOSHIBA

tên linh kiện	TMPR4925

Giải thích chi tiết về linh kiện	64-Bit TX System RISC TX49 Family

PDF	590 Pages

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nhà sản xuất	TOSHIBA [Toshiba Semiconductor]

Trang chủ	http://www.semicon.toshiba.co.jp/eng

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Chapter 9 SDRAM Controller

9-18

9.4.4

SyncFlash Command Register (SFCMD)

0x8030

Reserved

: Type

: Initial

value

CCE

Reserved

R/W

:Type

0x0

0x00

: Initial

value

Bits

Mnemonic

Field Name

Description

31:16



Reserved



15:12

CCE

Command

Channel Enable

Command Channel Enable (Initial value: 0x0, R/W)

Setting one of these bits to “1” enables the command of the corresponding channel.

This command is simultaneously executed on all channels that are enabled.

Bit 15: Channel 3

Bit 14: Channel 2

Bit 13: Channel 1

Bit 12: Channel 0

11:10



Reserved



9:8

Bank Address

Bank Address (Initial value: 00, R/W)

The value is used as Bank Address in the LCR cycle of the SyncFlash command

sequence.

The value in this field is outputs to ADDR[19:18]

7:0

CMD

Command

Command (Initial value: 0x00, R/W)

The value is used as command in the LCR cycle of the SyncFlash command

sequence.

The value in this field is outputs to ADDR[12:5]

Figure 9.4.4 SyncFlash Command Register

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