TMPR4925 datasheet(194/590 Pages) TOSHIBA

194 / 590 page

Chapter 8 DMA Controller

8-24

8.4.2

DMA Channel Control Register (DMCCRn)

0xB018 (ch. 0)

0xB038 (ch. 1)

0xB058 (ch. 2)

0xB078 (ch. 3)

Reserved

IMMCHN USEXFSZ

DBINH SBINH CHRST RVBYTE ACKPOL REQPL EGREQ CHDN

DNCTL

EXTRQ

R/W

R/W : Type

001

0000

: Initial value

STLTIME/INTRQD

INTENE INTENC INTENT CHNEN XFACT

Reserved

SMPCHN

XFSZ

MEMIO SNGAD

R/W

R/W : Type

000

00000

000

: Initial value

Bit

Mnemonic

Field Name

Description

31:30



Reserved



IMMCHN

Immediate Chain

Immediate Chain (Initial value: 0, R/W)

Selects the control method of bus ownership during chain transfer.

1: When the DMA transfer completes due to the current DMA Channel Register and

DMCCRn.CHNEN=1, DMA Command Descriptor of the address set in DMCHARn

is loaded to DMA channel Register without bus ownership release. (Chain

Transfer)

0: When the DMA transfer completes due to the current DMA Channel Register and

DMCCRn.CHNEN=1, DMA controller once releases the bus ownership. After that

it gets bus ownership again and starts Chain Transfer.

Note: It is not concerned with the setup of this bit but DMA controller releases bus

ownership after the Chain Transfer ends.

USEXFSZ

Transfer Set Size

Mode

Use Transfer Set Size (Initial value: 0, R/W)

Selects the DMA channel operation mode during Burst DMA transfer. Refer to

“8.3.7.2 Burst Transfer During Single Address Transfer” and “8.3.8.2 Burst Transfer

During Dual Address Transfer” for more information.

1: The DMA Controller always transfers the amount of data set in DMCCRn.XFSZ for

each bus operation. Since alignment to the boundary of the DMCCRn.XFSZ in the

address is not forced when in this mode, transfers that exceed 32 -word

boundaries are divided into two operations.

0: The DMA Controller calculates the transfer size so the address set in DMSARn

and DMDARn (only during Dual Address transfer) can be aligned to the boundary

of the size set in DMCCRn.XFSZ, then transfers data according to that size.

Little Endian

Little Endian (Default: value that is the opposite of the G-Bus Endian

(CCFG.ENDIAN))

This bit sets the Endian of the channel.

1: Channel operates in the Little Endian mode

0: Channel operates in the Big Endian mode

Figure 8.4.2 DMA Channel Control Register (1/4)

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