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TMPR4925 bảng dữ liệu(PDF) 130 Page - Toshiba Semiconductor

tên linh kiện TMPR4925
Giải thích chi tiết về linh kiện  64-Bit TX System RISC TX49 Family
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nhà sản xuất  TOSHIBA [Toshiba Semiconductor]
Trang chủ  http://www.semicon.toshiba.co.jp/eng
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TMPR4925 bảng dữ liệu(HTML) 130 Page - Toshiba Semiconductor

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Chapter 7 External Bus Controller
7-20
7.3.9.3
PCMCIA Channel Programming Requirements
Because of the multiple modes possible on a given EBUSC Channel the following restrictions
apply when a channel is used for PCMCIA access.
Page Mode is not allowed on a PCMCIA enabled Channel. Undetermined results will occur if
Page Mode is active.
External Ack Mode is not allowed on a PCMCIA enabled Channel. Undetermined results will
occur if External Ack Mode is active.
A channel that is used for PCMCIA access must be programmed to have a bus size of 16 or 8
bits. Addressing will not be correct if using a 32 bit bus size.
To meet the setup and hold timing of the PCMCIA bus the SHWT mode must be used.
Depending on the access speed of the card, the number of SHWT states and the speed of the
channel will need to be programmed to meet the timing requirements.
PWT and WT can be used to extend the OE*, WE*, CARDIORD*, and CARDIOWR* active
timing. See the description of the PWT and WT fields for details.
The EBUSC Controller can be used to implement the WAIT* function of the PCMCIA
specification. To do so PCMCIA channel must be programmed with the RDY bit set. See RDY
mode description for more details. Wait states will then be inserted externally until the WAIT*
signal from the PC card goes inactive and informing the EBUSC controller that it is READY. The
EBUSC controller supports a unique WAIT* signal for both slots. See device pin multiplexing for
details on support. The PWT/WT counter must be used programmed to account for the delay in
WAIT* valid from OE*, WE*, CARDIORD*, CARDIOWR*. Otherwise the high time of WAIT*
during this delay may cause the EBUSC controller to terminate the cycle early. The delay value
should take into account that the WAIT* signals are synchronized to the full speed clock
regardless of the speed of the channel.
7.3.9.4
PCMCIA Addressing and UAE
The PCMCIA specification has a 26 bit address bus. Since the external address bus of the
device is only 20 bits, the top 6 bits must be latched using the UAE signal. See the description on
UAE for more details.
The PCMCIA specification always uses a byte addressing scheme, where A0 is a “don’t care”
for “Word” and “Odd-Byte-Only” accesses. Normally the EBUSC controller outputs an address
that allows for addressing bytes, half words, or words depending on the programmed bus size. For
accessing data sizes smaller than the programmed bus size the BE*/BWE* signals are used in
normal operations. In the case of a channel being used for PCMCIA access the addressing will
always be for bytes, regardless of the bus size being 16 or 8 bit.



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