TMPR4925 datasheet(114/590 Pages) TOSHIBA

114 / 590 page

Chapter 7 External Bus Controller

7-4

7.3.2

Global/Boot-up Options

In addition to the settings made separately for each channel, the Channel Control Registers can also

use global options that make settings common to all channels.

External Bus Controller Channel 0 and 7 can be used as a Boot memory channel. Channel 0 and 7 is

set by the external pins (Boot pins) during reset.

These settings are summarized below in Table 7.3.1. (Please refer to “3.2 Boot Configuration” and

“5.2.1 Chip Configuration Register” for more information.)

Table 7.3.1 Global/Boot-up Options (1/2)

Pin Name

Set Register

Explanation



PCFG.ACKIN

Selects the operation mode of the ACK*/READY signal.

0 = ACK*/READY Dynamic mode (Default)

1 = ACK*/READY Static mode



CCFG.UAEHOLD

Sets the address hold time relative to the UAE signal.

0: Address changes simultaneous to deassertion of the UAE signal.

1: Address changes 1 clock cycle after deassertion of the UAE signal.

(Default)

ADDR[4:3]

CCFG.SYSSP

Specifies the division ratio of the SYSCLK output relative to the internal

bus clock (GBUSCLK).

00: 1/4 speed (1/4 the GBUSCLK frequency)

01: 1/3 speed (1/3 the GBUSCLK frequency)

10: 1/2 speed (1/2 the GBUSCLK frequency)

11: Full speed (same frequency as the GBUSCLK frequency)

EBCCR0.ME

Specifies whether to enable or disable Channel 0.

0: Disable this channel as a Boot channel. (ADDR[8] = 0)

1: Enable this channel as a Boot channel. (ADDR[8] = 1)

ADDR[8:6]

EBCCR0.SP

Specifies the operation speed of Channel 0.

00: 1/4 Speed mode (ADDR[8:6] = 100b)

01: 1/3 Speed mode (ADDR[8:6] = 101b)

10: 1/2 Speed mode (ADDR[8:6] = 110b)

11: Full Speed mode (ADDR[8:6] = 111b)

ADDR[11]

EBCCR0.BC

When accessing Channel 0, specifies whether to use the BWE[3:0] signal

as a Byte Enable signal (BE[3:0]) or to use it as a Byte Write Enable

signal (BWE[3:0]).

0: Byte Enable mode

1: Byte Write Enable mode

ADDR[5]

EBCCR0.EACK

Specifies the Channel 0 access mode.

0: Disable ACK* Input Mode (ADDR[5] = H)

1: Enable ACK* Input Mode

(ADDR[5] = L)

ADDR[13:12]

EBCCR0.BSZ

Specifies the memory bus width of Channel 0.

00: Reserved

01: 32-bit width

10: 16-bit width

11: 8-bit width

TMPR4925 bảng dữ liệu(PDF) 114 Page - Toshiba Semiconductor

TMPR4925 bảng dữ liệu(HTML) 114 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL