TMPR4925 datasheet(104/590 Pages) TOSHIBA

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Chapter 5 Configuration Register

5-14

5.2.10

GBUS Arbiter Control Register (GARBC)

0xE02C

Reserved

: Type

: Initial value

Reserved

ARBMD

R/W

: Type

0x00

1111

: Initial value

Bits

Mnemonic

Field Name

Description

31:13



Reserved



12:5



Reserved

Note: This bit is always set to “0” (Initial value: 0x00, R/W).



Reserved

Note: This bit is always set to “1” (Initial value: 1, R/W).

3:0

ARBMD

Arbitration Mode

Arbitration Priority (Initial value: 1111, R/W)

Specifies how to prioritize G-Bus arbitration.

0000: Fixed priority. The G-Bus arbitration priority conforms to the content of the

PRIORITY field (bits [14:0]).

1111: Round-robin (in a round-robin fashion, CHI > PDMAC > RTC > DMAC)

Others: Reserved (Don’t set these values.)

Note: Before accessing the PCI by DMAC, specify round-robin as the priority mode.

If fixed-priority mode is selected, a dead lock is likely to occur in PCI bus

access.

Figure 5.2.10 GBUS Arbiter Control Register (GARBC)

5.2.11

0xE030

Reserved

: Type

: Initial value

RAMP [31:16]

R/W

: Type

0xFF1F

: Initial value

Bits

Mnemonic

Field Name

Description

31:16



Reserved



15:0

RAMP[31:16]

Mapping

This is a base address register for the TX4925 built-in registers. It holds the high-

order 16 bits of a register address.

The default built-in register base address is 0xFFIF_0000. Even after the content of

the base address register is changed, the default value can be used to reference the

built-in registers.

(Refer to "4.2 Register Map".)

Figure 5.2.11 Register Address Mapping Register (RAMP)

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