S75WS256NDFBAWMB datasheet(112/216 Pages) SPANSION

112 / 216 page

110

S75WS256Nxx Based MCPs

S75WS-N-00_00_A0 February 17, 2005

Data

Sheet

See also the Requirements for Asynchronous Read Operation (Non-Burst) and the Requirements

for Synchronous (Burst) Read Operation sections for more information. The Asynchronous Read

and Synchronous/Burst Read tables provide the read parameters, Figure 25.2, Figure 25.3, and

Figure 25.7 show the timings.

19.2 Set Configuration Register Command Sequence

The device uses a configuration register to set the various burst parameters: number of wait

states, burst read mode, RDY configuration, and synchronous mode active. The configuration reg-

ister must be set before the device will enter burst mode.

The configuration register is loaded with a four-cycle command sequence. The first two cycles are

standard unlock sequences. On the third cycle, the data should be D0h and address bits should

be 555h. During the fourth cycle, the configuration code should be entered onto the data bus with

the address bus set to address 000h or 001h. Once the data has been programmed into the con-

figuration register, a software reset command is required to set the device into the correct state.

The device will power up or after a hardware reset with the default setting, which is in asynchro-

nous mode. The register must be set before the device can enter synchronous mode. The

configuration register can not be changed during device operations (program, erase, or sector

lock).

19.3 Read Configuration Register Command Sequence

The configuration register can be read with a four-cycle command sequence. The first two cycles

are standard unlock sequences. On the third cycle, the data should be C6h and address bits

should be 555h. During the fourth cycle, the configuration code should be read out of the data

bus with the address bus set to address 000h or 001h. Once the data has been read from the

configuration register, a software reset command is required to set the device into array read

mode.

Figure 19.1 Synchronous/Asynchronous State Diagram

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Synchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(D15 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(D15 = 1)

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