MPC821 datasheet(182/242 Pages) NXP

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Hardware Preparation and Installation

MPC860TFADS Daughter Board Design Specification—Rev 0.1

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

FIGURE 2-2 U1 Power Sources

From looking at FIGURE 2-2 "U1 Power Sources" above, we see that 5V (with 3.3V output only!)

oscillator may be used with 14 pins only form-factor while 3.3V oscillators may be used with 8 pins

only form-factor.

WARNING

IF A 14 Pin Form-Factor, 3.3V Clock Generator is in-

serted to U1, PERMANENT DAMAGE Might Be In-

flicted To The Device.

WARNING

Since the MPC clock input is NOT 5V TOLERANT,

any clock generator inserted to U1, MUST HAVE

3.3V compatible output. If a 5V output clock gener-

ator is inserted to U1, PERMANENT DAMAGE

might be inflicted to the MPC.

2•3•2

Power-On Reset Source Selection

As there are differences between MPC revisions regarding the functionality of the Power-On Reset

logic, it is therefore necessary to select different sources for Power-ON reset generation.

J1 on the MPC860TFADSDB is used to select Power-On Reset source: when a jumper is placed

between positions 1 - 2 of J1, Power-On reset to the MPC is generated by the Keep-Alive power rail.

I.e., When KAPWR goes below 2.005V - Power-On reset is generated. When a jumper is place

between position 2 - 3 of J1, Power-On reset to the MPC is generated from the MAIN 3.3V power rail.

I.e, when the MAIN 3.3V power rail goes below 2.805V Power-On reset is generated.

GND

3.3V

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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