HC05RC17GRSSLASHD datasheet(90/128 Pages) NXP

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Phase-Locked Loop (PLL) Synthesizer

General Release Specification

MC68HC05RC17 — Rev. 2.0

Phase-Locked Loop (PLL) Synthesizer

PLLON — PLL On

This bit activates the synthesizer circuit without connecting it to the

control circuit. This allows the synthesizer to stabilize before it can

drive the CPU clocks. When this bit is cleared, the PLL is shut off and

the BCS bit cannot be set. (Setting the BCS bit would engage the

disabled PLL onto the bus). Reset sets this bit.

NOTE:

For minimum current consumption, disable the PLL module before

entering wait mode.

NOTE:

The PLLON bit should not be cleared unless the BCS bit has been

cleared on a previous write to the register.

VCOTST — VCO Test

NOTE:

This bit is intended for use by Freescale. This bit cannot be cleared in user

mode.

PS1 and PS0 — PLL Synthesizer Speed Select

These two bits select one of four taps from the PLL to drive the CPU

clocks. These bits are used in conjunction with PLLON and BCS bits

in the PLL control register. Reset clears PS1 and sets PS0, choosing

a bus clock frequency of 524 kHz using an external crystal of

32.768 kHz.

CAUTION:

This bit should not be modified if BCS and PLLON in the PLLCR are both

at a logic high.

Table 10-1. PS1 and PS0 Speed Selects

with 32.768-kHz Crystal

PS1

PS0

CPU Bus Clock

Frequency (fOP)

524 kHz

1.049 MHz

Reset Condition

2.097 MHz

For 3.0 V ≤ VDD ≤ 5.5 V

4.194 MHz

Do Not Select

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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