HC05RC17GRSSLASHD datasheet(44/128 Pages) NXP

44 / 128 page

Interrupts

General Release Specification

MC68HC05RC17 — Rev. 2.0

Interrupts

When edge sensitivity is selected for the IRQ interrupt, it is sensitive to

these cases:

1. Falling edge on the IRQ pin

2. Falling edge on any port B pin with pullup/interrupt enabled

When edge and level sensitivity is selected for the IRQ interrupt, it is

sensitive to these cases:

1. Low level on the IRQ pin

2. Falling edge on the IRQ pin

3. Falling edge or low level on any port B pin with pullup/interrupt

enabled

External interrupts also can be masked by setting the EIMSK bit in the

MSCR register of the IR remote timer. See 9.5.4 Modulator Period

Data Registers

for details.

4.8 External Interrupt Timing

If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts

(internal and external) are disabled. Clearing the I bit enables interrupts.

The interrupt request is latched immediately following the falling edge of

the IRQ source. It is then synchronized internally and serviced as

specified by the contents of $3FFA and $3FFB.

Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-

only trigger is available via the mask programmable option for the IRQ

pin.

4.9 Carrier Modulator Transmitter Interrupt (CMT)

A CMT interrupt occurs when the end-of-cycle flag (EOC) and the end-

of-cycle interrupt enable (EOCIE) bits are set in the modulator control

and status register (MCSR). This interrupt will vector to the interrupt

service routine located at the address specified by the contents of

memory locations $3FF8 and $3FF9.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC05RC17GRS/D bảng dữ liệu(PDF) 44 Page - NXP Semiconductors