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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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HC05RC17GRS/D bảng dữ liệu(PDF) 81 Page - NXP Semiconductors |
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HC05RC17GRS/D bảng dữ liệu(HTML) 81 Page - NXP Semiconductors |
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81 / 128 page  Carrier Modulator Transmitter (CMT) Modulator MC68HC05RC17 — Rev. 2.0 General Release Specification Carrier Modulator Transmitter (CMT) 9.5.3.1 End-of-Cycle (EOC) Interrupt At the end of each cycle (when the counter is reloaded from MBUFF), the end-of-cycle (EOC) flag is set. If the interrupt enable bit was previously set, an interrupt will also be issued to the CPU. The EOC interrupt provides a means for the user to reload new mark/space values into the MBUFF and SBUFF registers. As the EOC interrupt is coincident with reloading the counter, MBUFF does not require additional buffering and may be updated with a new value for the next period from within the EOC interrupt service routine (ISR). To allow both mark and space period values to be updated from within the same ISR, SREG is buffered by SBUFF. The contents written to SBUFF are transferred to the active register SREG at the end of every cycle irrespective of the state of the EOC flag. The EOC flag is cleared by a read of the modulator control and status register (MCSR) followed by an access of MDR2 or MDR3. The EOC flag must be cleared within the ISR to prevent another interrupt being generated after exiting the ISR. If the EOC interrupt is not being used (IE = 0), the EOC flag need not be cleared. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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