HC05RC17GRSSLASHD datasheet(56/128 Pages) NXP

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Low-Power Modes

General Release Specification

MC68HC05RC17 — Rev. 2.0

Low-Power Modes

Figure 6-1. Stop Recovery Timing Diagram

NOTE:

The EIMSK bit of the carrier modulator transmitter MCSR (modulator

control and status register) is not cleared automatically by the execution

of a STOP instruction. Care should be taken to clear this bit before

entering stop mode.

6.4 Wait Mode

The WAIT instruction places the MCU in a low power-consumption

mode, but wait mode consumes more power than stop mode. All CPU

action is suspended, but the core timer, the oscillator, and any enabled

module remain active. Any interrupt or reset will cause the MCU to exit

wait mode. The user must shut off subsystems to reduce power

consumption. Wait current specifications assume CPU operation only

and do not include current consumption by any other subsystems.

3FFE

3FFF

INTERNAL

ADDRESS

BUS

INTERNAL

CLOCK

IRQ3

IRQ2

RESET

OSC11

ILCH

4064 t

CYC

RESET OR INTERRUPT

VECTOR FETCH

LIH

NOTES:

1. Represents the internal gating of the OSC1 pin

2. IRQ pin edge-sensitive mask option

3. IRQ pin level and edge-sensitive mask option

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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