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HC05RC17GRS/D bảng dữ liệu(PDF) 34 Page - NXP Semiconductors

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Giải thích chi tiết về linh kiện  General Release Specification
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Central Processor Unit (CPU)
General Release Specification
MC68HC05RC17 — Rev. 2.0
Central Processor Unit (CPU)
3.3 CPU Registers
The MCU contains five registers as shown in Figure 3-1. The interrupt
stacking order is shown in Figure 3-2.
Figure 3-1. Programming Model
Figure 3-2. Stacking Order
A
70
X
70
HI
N
Z
C
CCR
11
SP
70
PC
13
0
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER
STACK POINTER
CONDITION CODE REGISTER
0
0
0
0
0
13
0
INDEX REGISTER
PCL
ACCUMULATOR
CONDITION CODE REGISTER
PCH
11
1
70
STACK
I
N
T
E
R
R
U
P
T
DECREASING
UNSTACK
R
E
T
U
R
N
INCREASING
NOTE:
Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
MEMORY
ADDRESSES
MEMORY
ADDRESSES
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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