MPC8308CVMADDA datasheet(12/95 Pages) NXP

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

DDR2 SDRAM

This figure illustrates the DDR2 input timing diagram showing the tDISKEW timing parameter.

Figure 4. Timing Diagram for tDISKEW

6.2.2

DDR2 SDRAM output AC timing specifications

Table 18. DDR2 SDRAM Output AC Timing Specifications

Parameter

Symbol 1

Min

Max

Unit

Notes

MCK[n] cycle time, MCK[n]/MCK[n] crossing

tMCK

7.5

ADDR/CMD output setup with respect to MCK

266 MHz

tDDKHAS

2.9

—

ADDR/CMD output hold with respect to MCK

266 MHz

tDDKHAX

2.33

—

MCS[n] output setup with respect to MCK

266 MHz

tDDKHCS

2.5

—

MCS[n] output hold with respect to MCK

266 MHz

tDDKHCX

3.15

—

MCK to MDQS Skew

tDDKHMH

–0.6

0.6

MDQ//MDM/MECC output setup with respect to

MDQS

266 MHz

tDDKHDS,

tDDKLDS

900

—

MDQ//MDM/MECC output hold with respect to

MDQS

266 MHz

tDDKHDX,

tDDKLDX

1100

—

MCK[n]

tMCK

MDQ[x]/

MDQS[n]

tDISKEW

MECC[x]

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