MPC8308CVMADDA datasheet(31/95 Pages) NXP

31 / 95 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

High-Speed Serial interfaces (HSSI)

Figure 21. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 22 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

MPC8308 SerDes reference clock input’s DC requirement, AC-coupling has to be used.

This figure assumes that the LVPECL clock driver’s output impedance is 50

R1 is used to DC-bias the

LVPECL outputs prior to AC-coupling. Its value could be ranged from 140

to 240 depending on clock

driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-



termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the

MPC8308’s SerDes reference clock’s differential input amplitude requirement (between 200 mV and

800 mV differential peak). For example, if the LVPECL output’s differential peak is 900 mV and the

desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which

requires R2 = 25

Please consult clock driver chip manufacturer to verify whether this connection

scheme is compatible with a particular clock driver chip.

Figure 22. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)



SD_REF_CLK

Clock Driver

100

differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8308



SD_REF_CLK

Clock Driver

100

differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK

Driver Chip

MPC8308

10nF

10 nF

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