MPC8308CVMADDA datasheet(21/95 Pages) NXP

21 / 95 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII management

8.3.2

MII Management AC electrical specifications

This table provides the MII management AC timing specifications.

Output low voltage

VOL

IOL = 1.0 mA

LVDD = Min

VSS

0.50

Input high voltage

VIH

—2.0

—

Input low voltage

VIL

—

0.80

Input high current

IIH

NVDD = Max

VIN

1 = 2.1 V

—

A

Input low current

IIL

NVDD = Max

VIN = 0.5 V

–600

—

A

Note:

1. VIN, in this case, represents the LVIN symbol referenced in Table 1 and Table 2.

Table 27. MII Management AC Timing Specifications

At recommended operating conditions with LVDDA/LVDDB is 3.3 V ± 0.3V

Parameter/Condition

Symbol 1

Min

Typ

Max

Unit

Notes

MDC frequency

fMDC

—2.5

—

MHz

MDC period

tMDC

—400

—

MDC clock pulse width high

tMDCH

—

MDC to MDIO delay

tMDKHDX

—

170

MDIO to MDC setup time

tMDDVKH

5—

—

MDIO to MDC hold time

tMDDXKH

0—

—

MDC rise time

tMDCR

——

—

MDC fall time

tMDHF

——

—

Notes:

1. The symbols used for timing specifications Follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management

data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter

convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt Clock Select] field determines the clock frequency

of the Mgmt Clock EC_MDC.)

3. This parameter is dependent on the cbs_clk speed (that is, for a csb_clk of 133 MHz, the delay is 60 ns).

Table 26. MII Management DC Electrical Characteristics When Powered at 3.3 V (continued)

Parameter

Symbol

Conditions

Min

Max

Unit

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