MPC8308CVMADDA datasheet(51/95 Pages) NXP

51 / 95 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

JTAG

This figure provides the AC test load for TDO and the boundary-scan outputs.

Figure 40. AC Test Load for the JTAG Interface

This figure provides the JTAG clock input timing diagram.

Figure 41. JTAG Clock Input Timing Diagram

Output hold times:

Boundary-scan data

TDO

tJTKLDX

tJTKLOX

—

JTAG external clock to output high impedance:

Boundary-scan data

TDO

tJTKLDZ

tJTKLOZ

5, 6

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.

The output timings are measured at the pins. All output timings assume a purely resistive 50-

load (see Figure 40).

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device

timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)

going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals

(D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference

symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the

latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to tTCLK.

5. Non-JTAG signal output timing with respect to tTCLK.

6. Guaranteed by design and characterization.

Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1 (continued)

At recommended operating conditions (see Table 2).

Parameter

Symbol2

Min

Max

Unit

Note

Output

Z0 = 50 

NVDD/2

RL = 50 

JTAG

tJTKHKL

tJTGR

External Clock

tJTG

tJTGF

VM = Midpoint Voltage (NVDD/2)

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