MPC8308CVMADDA datasheet(41/95 Pages) NXP

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

Enhanced Local Bus

NOTE

The reference impedance for return loss measurements is 50

 to ground for

both the D+ and D- line (that is, as measured by a Vector Network Analyzer

with 50

 probes—see Figure 29). Note that the series capacitors,

CPEACCTX, are optional for the return loss measurement.

Figure 28. Minimum Receiver Eye Timing and Voltage Compliance Specification

11.5.1

Compliance Test and Measurement Load

The AC timing and voltage parameters must be verified at the measurement point, as specified within

0.2 inches of the package pins, into a test/measurement load shown in Figure 29.

NOTE

The allowance of the measurement point to be within 0.2 inches of the

package pins is meant to acknowledge that package/board routing may

benefit from D+ and D– not being exactly matched in length at the package

pin boundary.

Figure 29. Compliance Test/Measurement Load

12 Enhanced Local Bus

This section describes the DC and AC electrical specifications for the enhanced local bus interface.

VRX-DIFFp-p-MIN > 175 mV

0.4 UI = TRX-EYE-MIN

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

VRX-DIFF = 0 mV

(D+ D– Crossing Point)

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